1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to an insulated gate field effect transistor characterized by its gate electrode, and to a method of manufacturing the same.
2. Description of the Related Art
In insulated gate field effect transistors used for current semiconductor integrated circuits, a polycrystalline silicon layer doped with high concentration of impurities is generally used as a gate electrode in order to decrease the resistance. In a semiconductor process used for CMOS circuits (Complimentary MOSFET circuits), N-type polycrystalline silicon and P-type polycrystalline silicon are respectively used for an N-channel MOSFET (NMOSFET) and a P-channel MOSFET (PMOSFET) as gate electrode materials for balancing the characteristics. Generally, a refractory metal silicide layer is formed in the upper layer of the gate electrode in order to further decrease the resistance.
However, depletion occurs in the polysilicon layer of the gate electrode although the polysilicon layer is doped with high concentration of impurities. Occurrence of depletion is equivalent to the condition in which a capacitance is inserted into the gate electrode in series, thereby decreasing an effective electric field applied to a channel. As a result, the current drive capability of the MOSFET decreases. It is difficult to decrease the resistance of the entire gate electrode to 5xcexa9/xe2x96xa1 or less even if a silicide layer is laminated on the polycrystalline silicon layer. In the case of miniaturizing the device to the 0.1 micron generation, since the thickness of the gate electrode must be reduced, the gate electrode is required to have a specific resistance of about 30 xcexcxcexa9xc2x7cm or less.
The work functions of the N-type polycrystalline silicon layer and the P-type polycrystalline silicon layer, which are directly in contact with the gate insulation layer, are respectively 4.15 eV and 5.25 eV. The work functions of these layers significantly differ from the center of the bandgap of silicon (4.61 eV). Such a large difference results in an increase in the absolute value of a flat band voltage VFB in a MOS capacitor formed of a metal-insulation layer-semiconductor (signs differ between NMOSFET and PMOSFET). Therefore, in such MOSFETs, an optimum value of the impurity concentration in the channel must be shifted to the high concentration side in order to control a threshold value VTH. The channel with high-concentration impurities is significantly influenced by carrier scattering due to impurities. As a result, carrier mobility in the channel decreases. This means a decrease in the current drive capability of the MOSFET, thereby significantly affecting the response characteristics of the circuit.
In order to solve these problems, low-resistance gate electrode materials which do not cause gate depletion to occur and have various work functions have been proposed. For example, Jeong-Mo Hwang, et al. (IEDM Technical Digest 1992, page 345) discloses a structure using a titanium nitride (TiN) layer. Ushiki, et al. (IEDM Technical Digest 1996, page 117) discloses a structure using a beta-tantalum (xcex2-Ta) layer.
The following is pointed out for the gate electrode having a TiN layer formed on a gate insulation layer used in the N-type or P-type MOSFET. Since the TiN layer has a relatively high specific resistance of about 200 xcexcxcexa9xc2x7cm, a metal (tungsten, for example) layer is laminated on the TiN layer in order to decrease resistance of the gate electrode. The work function of the TiN layer (4.7 to 4.8 eV) is close to the center of the bandgap of silicon (4.61 eV), as reported by Jeong-Mo Hwang, et al., whereby a significant effect is expected in view of the threshold value control.
However, according to this configuration example, since the TiN layer and the tungsten layer are dissolved in a chemical solution such as a hydrogen peroxide aqueous solution and sulfuric acid, it is very difficult to clean the gate electrode layer after etching. Therefore, devices having this structure cannot be manufactured at high yield.
The following is pointed out for the gate electrode having a tantalum layer formed on the gate insulation layer used in the N-type or P-type MOSFET. According to this configuration example, only a beta-tantalum layer exhibiting high resistance as a metal (specific resistance: about 160 xcexcxcexa9xc2x7cm) can be deposited as the tantalum layer, whereby the resistance of the gate electrode relatively increases. Moreover, since the work function of the beta-tantalum layer significantly differs from the center of the bandgap of silicon, the threshold value is shifted to the low threshold side, thereby resulting in an imbalance threshold between the NMOSFET and the PMOSFET.
An objective of the present invention is to provide a semiconductor device which exhibits high current drive capability and can be manufactured at high yield, and a method of manufacturing the same.
A semiconductor device according to one aspect of the present invention comprises:
first and second impurity diffusion layers forming a source region and a drain region which are formed in a semiconductor layer;
a channel region formed between the first and second impurity diffusion layers;
a gate insulation layer formed at least on the channel region; and
a gate electrode formed on the gate insulation layer,
wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer.
The semiconductor device according to this aspect of the present invention has the following actions and effects.
(1) The gate electrode includes the tantalum nitride layer formed so as to be in contact with the gate insulation layer. The work function of the tantalum nitride layer is approximately 4.5 eV, which is extremely close to the center of the bandgap of silicon. As a result, the absolute value of a flat band voltage in a capacitor formed of metal-insulation layer-silicon can be decreased. This eliminates the need for increasing the concentration of impurities doped into the channel region in order to obtain an appropriate threshold value. Therefore, a decrease in carrier mobility can be prevented, whereby a insulated gate field effect transistor exhibiting high current drive capability can be obtained at high yield.
(2) As described in the above (1), the work function of the tantalum nitride layer is extremely close to the center of the bandgap of silicon. Because of this, the difference in the absolute values of the flat band voltages between an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor can be significantly decreased in a capacitor formed of metal-insulation layer-silicon, although the same type of electrode is used for the both transistors. As a result, in a complementary semiconductor device including both an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the threshold balance between these transistors can be accurately and easily controlled. Moreover, use of the same type of the electrode reduces the fabrication steps in comparison with above-described conventional polysilicon gates. Furthermore, in the case of a complementary semiconductor device using a fully depleted silicon on insulator (SOI) structure or silicon on nothing (SON) structure, the absolute value of the threshold voltage can be decreased while preventing punch-through from occurring. This leads to advantages in miniaturization and low-voltage drive.
(3) The gate electrode includes at least the tantalum nitride layer, and the polysilicon layer is not in contact with the gate electrode. Therefore, depletion does not occur in the gate electrode. As a result, the gate electrode can prevent effective electric field applied to the channel region from decreasing in comparison with the case of using a polysilicon layer. This also prevents a decrease in current drive capability.
(4) The tantalum nitride layer forming the gate electrode exhibits higher chemical stability in comparison with a titanium nitride layer and the like. For example, the tantalum nitride layer exhibits excellent resistance to a chemical solution used to clean the gate electrode. As a result, devices can be manufactured at high yield.
This aspect of the present invention has the following features. These features also apply to a complementary semiconductor device and a method of manufacturing a semiconductor device described later.
(A) A nitrogen/tantalum ratio (x) shown by TaNx in the tantalum nitride layer may be 0.25 to 1.0 in view of conductivity and work function. In particular, the nitrogen/tantalum ratio (x) shown by TaNx in the tantalum nitride layer may be about 0.5.
(B) The gate electrode may be formed of a single layer formed of a tantalum nitride layer. In this case, the tantalum nitride layer may have a thickness of 1 nm to 300 nm in view of conductivity of the gate electrode.
(C) The gate electrode may have a multilayer structure including the tantalum nitride layer and a metal layer. As examples of the metal used for the metal layer, refractory metals such as tantalum, tungsten, molybdenum, the chromium, niobium, and vanadium can be given.
(D) The gate electrode may include a cap layer formed in the uppermost layer. The cap layer may be formed of at least one material selected from TaNx, TaSixNy, TiNx, TiAlxNy, Si, and silicide of a transition metal.
(E) Silicide layers may be formed on the exposed areas of the first and second impurity diffusion layers and on the upper side of the gate electrode. The presence of such silicide layers increases conductivity of the first and second impurity diffusion layers and the gate electrode.
(F) The semiconductor layer may have an SOI structure or SON structure. And the semiconductor layer may be a silicon layer containing impurities at a concentration of 1017 cmxe2x88x923 or less and having a thickness one-third a gate length or less, which is formed on a bulk semiconductor substrate containing impurities at a concentration of more than 1017 cmxe2x88x923.
The present invention can be suitably applied to a complementary semiconductor device, as described above. Specifically, a complementary semiconductor device according to another aspect of the present invention comprises an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor,
wherein each of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor includes:
first and second impurity diffusion layers for forming a source region and a drain region which are formed in a semiconductor layer;
a channel region formed between the first and second impurity diffusion layers;
a gate insulation layer formed on the channel region; and
a gate electrode formed on the gate insulation layer, and
wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer.
According to this complementary semiconductor device, since the work function of the tantalum nitride layer is extremely close to the center of the bandgap of silicon, as described above, the absolute value of the flat band voltage can be decreased. This eliminates the need for increasing the concentration of impurities doped into the channel region in order to obtain an appropriate threshold value. Therefore, a decrease in carrier mobility can be prevented, whereby a insulated gate field effect transistor exhibiting high current drive capability can be obtained at high yield. Moreover, the threshold balance between the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor can be accurately and easily controlled although the same type of electrode is used for the both transistors. Furthermore, in the case of a complementary semiconductor device using a fully depleted SOI structure or SON structure, the absolute value of the threshold voltage can be decreased while preventing punch-through from occurring. This ensures the achievement of miniaturization and low-voltage drive.
A method of manufacturing a semiconductor device according to a further aspect of the present invention comprises the following steps (a) to (c):
(a) a step of forming a gate insulation layer on a semiconductor layer;
(b) a step of forming a gate electrode on the gate insulation layer, and forming a tantalum nitride layer in a region in contact with at least the gate insulation layer; and
(c) a step of forming first and second impurity diffusion layers forming a source region and a drain region by introducing impurities into the semiconductor layer.
The method of manufacturing a semiconductor device according to this aspect of the present invention has the following features. These features also apply to a method of manufacturing a complementary semiconductor device described later.
(A) In the step (c), the first and second impurity diffusion layers may be formed in a self-alignment manner using the gate electrode as a mask
(B) The method may comprise a step (e) of forming a side-wall spacer on a side of the gate electrode after the step (c).
(C) Silicide layers may be formed on exposed areas of the first and second impurity diffusion layers after the step (e).
A method of manufacturing a complementary semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor according to a still further aspect of the present invention comprises the following steps (a) to (c):
(a) a step of forming a gate insulation layer on a semiconductor layer;
(b) a step of forming a gate electrode on the gate insulation layer, and forming a tantalum nitride layer in a region in contact with at least the gate insulation layer; and
(c) a step of introducing impurities into the semiconductor layer to form a source region and a drain region, comprising forming N-type first and second impurity diffusion layers for the N-channel insulated gate field effect transistor and forming P-type first and second impurity diffusion layers for the P-channel insulated gate field effect transistor.